1. Field of Invention
The invention relates to manufacture of an integrated circuit, in particular, to a method for etching a Mo-based metal gate stack with an aluminium nitride barrier.
2. Description of Prior Art
As critical dimension of a semiconductor device is reduced to 45 nm or beyond, it is a necessary choice to replace a conventional SiO2/polysilicon gate stack with a high dielectric constant (K) dielectric/metal gate stack so as to reduce direct tunneling current and a power consumption, and avoid poly-Si gate depletion effect and reliability issue due to B penetration in a P-type metal-oxide-semiconductor field effect transistor (MOSFET), and alleviate Fermi level pinning effect.
For a nano-scale CMOS device incorporating a high K dielectridmetal gate stack, work functions of a N-type MOSFET and a P-type MOSFET should be tuned to be near a conduction band bottom (about 4.1 eV) of Si and a valence band top (about 5.2 eV) of Si respectively, for improving in a short channel effect and getting a suitable threshold. A metal gate of Mo has a low resistivity (5×10−6Ω·cm) and a high melt point (above 2600° C.). Also, Mo metal gate with (110) orientation exhibits a high work function at about 5 eV, and thus it is a competitive candidate of a gate material of a P-type MOSFET. In addition, in order to facilitate the integration of high-k dielectrics and metal gates, one widely used approach is to use a gate stack with a thin metal gate layer inserted between a high-k dielectric and polysilicon (i.e. a silicon gate/metal gate stack) in place of a pure metal gate, so that a dry etching process can performed easily and it will increase the complexity of the existing CMOS process slightly. However, Mo metal gate will react with a silicon gate if the silicon gate is directly deposited on the metal gate of Mo at a high temperature. The inventor has solved this problem by adding a barrier layer of metal nitride which has a desired thermal stability between the metal gate of Mo and the silicon gate so as to improve a thermal reliability of the gate stack. Although adding the barrier layer solves the problem of a poor thermal stability, it causes a difficulty in etching the high K dielectric/metal gate structure. Thus, the integration of the metal gate of Mo into the P-type MOSFET needs an improved etching process for a barrier layer/metal gate of Mo stacked structure.